This invention pertains to multiplexers, and more particularly to a high-speed multiplexer having independent "one/zero" and "odd/even" adjustments for minimizing the bit error rate of a multiplexed signal.
Any digital signal, such as a data transmission output signal, is comprised of many transitions between a logic zero level and a logic one level over time. In characterizing the error rate of a data transmission system, multiple output signal waveforms responsive to multiple input conditions are overlayed. The overlayed output signal waveforms comprise the well known "eye pattern." The various transitions from the logic zero level to the logic one level and from the logic one level to the logic zero level in the eye pattern intersect at crossing points. The crossing points of the overlayed waveform can be characterized in both time and amplitude. The time and amplitude information of the crossing points in the eye pattern is highly correlated with the overall data transmission system bit error rate. In a system having low error, the crossing points are spaced at equal intervals in time (50% duty cycle), and the crossing points occur halfway between the logic zero level and the logic one level in amplitude.
Similarly, for a multiplexed digital signal, comprising sequential components of two or more distinct digital signals, it is important that the error introduced by the multiplexer itself be characterized and, if possible, reduced or eliminated.
Referring now to FIG. 1, the performance of a two-to-one multiplexer is characterized in time by displaying a composite output waveform. The output waveform is comprised of first and second input signals, each alternatively selected during sequential time intervals T.sub.ODD and T.sub.EVEN. The transition from selecting the first input signal to the second input signal is controlled by the multiplexer and the circuit that causes the multiplexer to switch. In an ideal multiplexer output signal, each of the first and second input signals is alternatively selected during sequential time intervals. Transitions from a logic zero to a logic one and transitions from a logic one to a logic zero for both time intervals are shown to display three crossing points. Horizontal lines indicating transitions between a logic zero and a logic zero, and transitions between a logic one and a logic one, which normally complete the eye pattern, are not shown for clarity. An ideal multiplexer output waveform is shown in solid lines, and a non-ideal, odd/even time skewed multiplexer output waveform is shown in dashed lines. In the ideal waveform, the times between consecutive crossing points, T.sub.ODD1 and T.sub.EVEN1, are equal. The total of T.sub.ODD1 and T.sub.EVEN1 defines a total time equal to T. In the non-ideal waveform, the times between consecutive crossing points, T.sub.ODD2 and T.sub.EVEN2, are not equal although the total of T.sub.ODD2 and T.sub.EVEN2 is still equal to T.
Referring now to FIG. 2, the performance of a two-to-one multiplexer is further characterized in time by the amplitude of the crossing points displayed in the composite output waveform. The ideal multiplexer output waveform is again shown in solid lines, and the non-ideal, one/zero time skewed multiplexer output waveform is shown in dashed lines. In the ideal waveform, the consecutive crossing points occur at the threshold voltage V.sub.CROSS1, which is halfway between the logic zero level, V.sub.ZERO, and the logic one level, V.sub.ONE. In the non-ideal waveform, the consecutive crossing points occur at a threshold voltage V.sub.CROSS2, which is either more positive or more negative than halfway between the logic zero level and the logic one level.
In either the ideal case or the non-ideal case shown in FIG. 2, the total time interval for one cycle of the multiplexed output waveform is still equal to T (T.sub.ODD plus T.sub.EVEN) from crossing point t.sub.1 to crossing point t.sub.3. However, at the threshold voltage V.sub.CROSS1, the non-ideal waveform still has equal time intervals T.sub.ODD and T.sub.EVEN, but these time intervals are each less than 50% of the total cycle to complete the multiplexing of the two input signals. This timing error is significant for logic blocks coupled to the output of the multiplexer, which will trigger at the V.sub.CROSS1 threshold voltage and not the V.sub.CROSS2 threshold voltage.
Both the odd/even and one/zero timing errors shown in FIGS. 1 and 2 can be caused by offset voltage, rise and fall time mismatches, as well as other random device mismatches.
It is important to note that the performance of the multiplexer is degraded in time both by clock skew timing (odd/even) errors associated with the switching of the multiplexer and by crossing point amplitude timing (one/zero) errors occurring at the output of the multiplexer and affecting circuits coupled to the output. Each of these timing error components are independent, and each contributes to closing the eye pattern and increasing the bit error rate. The errors can be generated in the clock signal, in the multiplexer itself, in the output stage, and in subsequent circuits coupled to the output of the multiplexer.
Therefore, what is desired is a multiplexer that has independent odd/even and one/zero adjustments for cancelling out both clock skew and crossing point timing errors in order to minimize the bit error rate of the multiplexed output signal.